Wisconsin Discovery Portal

Researcher: Karthikeyan (Karu) Sankaralingam

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Areas of Expertise
  • Artificial intelligence
  • Computational biology
  • Architecture
  • Graphics
  • Networks
  • Security
  • Database systems
  • Human-computer interaction
  • Optimization
  • Programming languages
  • Microarchitecture
  • Software issues for massively parallel computation systems
  • Technology driven microarchitecture constraints
  • Concurrency requirements and methods of expressing concurrency at architecture, compiler, and language level
  • Application analysis
  • Application trends influencing microarchitecture and architecture
  • Mobility, ultra-small factors with high computation requirements
Web Site Karu Sankaralingam's Department of Computer Sciences Website
Curriculum Vitae (CV) Karu Sankaralingam's CV
Issued Patent(s)
  • 9,384,858 - Computer system predicting memory failure, issued July 2016.
  • 9,384,016 - Method of estimating program speed-up with highly parallel architectures, issued July 2016.
  • 9,298,497 - Computer processor providing exception handling with reduced state storage, issued March 2016.
  • 9,244,772 - Computer processor providing error recovery with idempotent regions, issued January 2016.
  • 9,231,865 - Lookup engine with reconfigurable low latency computational tiles, issued January 2016.
USPTO Published Applications
  • 20160170765 - Computer processor providing exception handling with reduced state storage, published June 2016.
  • 20160148707 - Computer system predicting memory failure, published May 2016.
  • 20160041856 - Memory processing core architecture, published February 2016.
  • 20150261536 - Method of estimating program speed-up with highly parallel architectures, published September 2015.
  • 20150261528 - Computer accelerator system with improved efficiency, published September 2015.
Recent Publication(s)
  • Pushing the limits of accelerator efficiency while retaining programmability. Nowatzki T, Gangadhan V, Sankaralingam K, Wright G. 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA). 2016 Mar 12:27-39. doi: 10.1109/HPCA.2016.7446051.

  • Near-memory data services. Falsafi B, Stan M, Skadron K, Jatasena N, Y Chen, et al. IEEE Micro. 2016 Feb 25;36(1):6-13. doi: 10.1109/MM.2016.9.

  • Dark silicon and the end of multicore scaling. Esmaeilzadeh H, Blem E, St. Amant R, Sankaralingam K, D Burger. IEEE Micro. 2016 May 30;32(3):122-134. doi: 10.1109/MM.2012.17.

  • A heterogeneous von neumann/explicit dataflow processor. Nowatzki T, Gangadhar V, Sankaralingam K. IEEE Micro. 2016 Jun 7;36(3):20-30. doi: 10.1109/MM.2016.34.


View Karu Sankaralingam's publications at Google scholar.
Recent Artistic Works
Collaboration
  • University of Texas-Austin
Research Tools
Research Facilities
E-mail Address [email protected]
Phone Number 608-890-0121
Current University UW–Madison
Department Computer Sciences
Title Associate Professor
Other Appointments
Address Line 1 6367 Computer Sciences and Statistics
Address Line 2 1210 West Dayton Street
City Madison
State WI
Zip Code 53706
Bachelor's Degree B.tech., Indian Institute of Technology, 1999
Master's Degree M.S., University of Texas-Austin, Computer Science, 2006
PhD Ph.D., University of Texas-Austin, Computer Science, 2006
Other Degrees
Technologies Available for Licensing Pipelined Lookup Grid Architecture (PLUG)–Fast, Cool and Flexible Network Processing

Computer Accelerator System Boosts Efficiency

Method Predicts Porting Speedup

Memory Processing Unit Boosts Performance, Cuts Energy Usage

Predicting Logic Gate Failure

Predicting Computer Memory Failure

Computer Architecture Enables Simplified Recovery from Speculative Execution Errors without Checkpoints

More Efficient, Portable Graphic Processing System by Exception Handling

LEAP - Improved Data Lookup for High-Speed Routers