Wisconsin Discovery Portal

Researcher: Gurindar Sohi

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Areas of Expertise
  • Artificial intelligence
  • Computational biology
  • Architecture
  • Graphics
  • Networks
  • Security
  • Database systems
  • Human-computer interaction
  • Optimization
  • Programming languages
  • Design of high-performance computer systems
  • Thread-level speculation
  • High bandwidth data memory systems for superscalar processors
  • Dynamically-scheduled processor
  • Design of uniprocessors and memory systems
  • Multiscalar paradigm
  • Program behavior
  • Develop generic mechanisms to exploit program behavior
  • Memory systems to support multiscalar processing
  • Memory hierarchy organizations for the billion transistor era
Web Site Gurindar Sohi's Department of Computer Sciences Website
Curriculum Vitae (CV)
Issued Patent(s)
  • 9,223,717 - Computer cache system providing multi-line invalidation messages, issued December 2015.
  • 8,843,932 - System and method for controlling excessive parallelism in multiprocessor systems, issued September 2014.
  • 8,417,919 - Assigning different serialization identifier to operations on different data set for execution in respective processor in multi-processor system, issued April 2013.
  • 9,223,674 - Computer system and method for runtime control of parallelism in program execution, issued December 2015.
  • 7,962,774 - Over-provisioned multicore processor, issued June 2011.
USPTO Published Applications
  • 20160188486 - Cache accessed using virtual addresses, published June 2016.
  • 20140229704 - Precise-restartable parallel execution of programs, published August 2014.
  • 20140101390 - Computer cache system providing multi-line invalidation messages, published April 2014.
  • 20120180062 - System and method for controlling excessive parallelism in multiprocessor systems, published July 2012.
  • 20120066690 - System and method providing run-time parallelization of computer software using data associated tokens, published March 2012.
Recent Publication(s)
  • Revisiting virtual L1 caches: A practical design using dynamic synonym remapping. Yoon H, Sohi GS. 2016 IEEE HPCA. 2016 Mar 12:212-224. doi: 10.1109/HPCA.2016.7446066.

  • Supporting overcommitted virtual machines through hardware spin detection. Chakraborty K, Wells PM, Sohi GS. IEEE Transactions on Parallel and Distributed Systems. 2011 Dec 26;23(2):353-366. doi: 10.1109/TPDS.2011.143.

  • Efficient, precise-restartable program execution on future multicores. Gupta G, Sridharan S, Sohi GS. 2012 IEEE Hot Chips 24 Symposium (HCS). 2012 Aug 27:1-3. doi: 10.1109/HOTCHIPS.2012.7476510.

  • Adaptive, efficient, parallel execution of parallel programs. Sridharan S, Gupta G, Sohi GS. ACM SIGPLAN Notices. 2014 Jun;49(6). doi: 10.1145/2594291.2594292.
Recent Artistic Works
Collaboration
  • University of Toronto, Electrical & Computer Engineering
  • University of Texas, Computer Sciences
Research Tools
  • TETRA: A Multi-platform Instruction Trace Analyzer
  • SimpleScalar: Tools for simulation of modern processors
Research Facilities
E-mail Address [email protected]
Phone Number 608-262-7985
Current University UW–Madison
Department Computer Sciences
Title Professor
Other Appointments
Address Line 1 6375 Computer Sciences and Statistics
Address Line 2 1210 West Dayton Street
City Madison
State WI
Zip Code 53706
Bachelor's Degree
Master's Degree
PhD Ph.D., University of Illinois, Electrical and Computer Engineering, 1985
Other Degrees
Technologies Available for Licensing Method and Device for Parallel Execution of Computer Software Using a Distilled Program

Data Flow Execution of Methods in Sequential Programs

Over-Provisioned Multicore Processor Computing System

Controlling Parallelism in Real Time

Dynamic Dependence-Based Parallel Execution of Software for Performance Optimization

Optimizing Parallelism During Run-Time

Memory Bypass Circuit for Faster Data Transfer

Cache Memory System to Reduce Invalidation Message Traffic

Improved Method Provides Run-Time Parallelization of Computer Software

Precise Restarts for Handling Interrupts in Parallel Processing