Wisconsin Discovery Portal

Researcher: Kewal Saluja

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Areas of Expertise
  • Applied physics
  • Computing
  • Information
  • Power
  • Design for testability
  • Computer architecture
  • Built-in self-test
  • VLSI design and testing
  • Fault-tolerant computing
  • Digital circuits
  • Switching theory
  • Logic design
  • Control systems
  • Computer organization
  • Microprocessor systems
Web Site Kewal Saluja's Department of Electrical and Computer Engineering Website
Curriculum Vitae (CV)
Issued Patent(s)
  • 8,533,548 - Wrapper cell for hierarchical system on chip testing, issued September 2013.
  • 7,665,001 - Progressive random access scan circuitry, issued February 2010.
USPTO Published Applications
  • 20120124439 - Wrapper cell for hierarchical system on chip testing, published May 2012.
  • 20080091995 - Progressive random access scan circuitry, published April 2008.
Recent Publication(s)
  • Digital testing -- Basics to advanced research issues. Saluja K. 2016 29th International Conference on VLSI Design. 2016 Jan 4:1-11. doi: 10.1109/VLSID.2016.132.

  • CryptIP: An approach for encrypting intellectual property cores with simulation capabilities. Millican S, Ramanathan P, Saluja K. 2014 27th International Conference on VLSI Design. 2014 Jan 5:92-97. doi: 10.1109/VLSID.2014.23.

  • Scheduling aperiodic tasks in next generation embedded real-time systems. Ahmed R, Ramanathan P, Saluja KK, Yao C. 2013 26th International Conference on VLSI Design. 2013 Jan 5:25-30. doi: 10.1109/VLSID.2013.157.

  • Impact of body bias based leakage power reduction on soft error rate. Sootkaneung W, Saluja KK. 2012 25th International Conference on VLSI Design. 2012 Jan 7:74-79. doi: 10.1109/VLSID.2012.49.


View Kewal Saluja's publications at Google scholar.
Recent Artistic Works
Collaboration
  • Nara Institute of Science & Technology (Japan)
  • Kyushu Institute of Technology (Japan)
  • Japan Science and Technology Agency
  • SynTest Technology Inc.
  • Osaka Gakuin University (Japan)
Research Tools
Research Facilities
E-mail Address [email protected]
Phone Number 608-262-6490
Current University UW–Madison
Department Electrical and Computer Engineering
Title Emeritus Professor
Other Appointments
Associate Editor, Journal of Electronic Testing: Theory and Applications (JETTA)
Editorial Board, IEEE Transactions on Computers
Address Line 1 4611 Engineering Hall
Address Line 2 1415 Engineering Drive
City Madison
State WI
Zip Code 53706
Bachelor's Degree B.E., University of Roorkee, India, 1967
Master's Degree M.S., University of Iowa, 1972
PhD Ph.D., University of Iowa, 1973
Other Degrees
Technologies Available for Licensing Progressive Random Access Scan Circuitry

Wrapper Cell for Hierarchical System-on-Chip Testing

Encrypting Intellectual Property Cores