Wisconsin Discovery Portal

Researcher: Michael Schulte

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Areas of Expertise
  • Applied physics
  • Computing
  • Information
  • Power
  • Domain-specific processor design
  • Reconfigurable computing
  • Computer arithmetic
  • Computer architecture
  • Embedded systems
  • High-performance, low-power embedded processors
  • Network processor architectures
  • Processor support for decimal floating-point arithmetic
  • 4D cluster visualization
Web Site Michael Schulte's Department of Electrical and Computer Engineering Website
Curriculum Vitae (CV)
Issued Patent(s)
  • 8,959,315 - Multithreaded processor with multiple concurrent pipelines per thread, issued February 2015.
  • 7,962,543 - Division with rectangular multiplier supporting multiple precisions and operand types, issued June 2011.
  • 7,797,363 - Processor having parallel vector multiply and reduce operations with sequential semantics, issued September 2010.
  • 7,743,084 - Processing unit having multioperand decimal addition, issued June 2010.
  • 7,593,978 - Processor reduction unit for accumulation of multiple operands with or without saturation, issued September 2009.
USPTO Published Applications
  • 20140068304 - Method and apparatus for power reduction during lane divergence, published March 2014.
  • 20120096243 - Multithreaded processor with multiple concurrent pipelines per thread, published April 2012.
  • 20090276432 - Data file storing multiple data types with controlled data access, published November 2009.
  • 20080301213 - Division with rectangular multiplier supporting multiple precisions and operand types, published December 2008.
  • 20060095729 - Multithreaded processor with multiple concurrent pipelines per thread, published May 2006.
Recent Publication(s)
  • Achieving exascale capabilities through heterogeneous computing. Schulte MJ, Ignatowski MJ, Loh GH, Beckmann BM, Brantley WC, et al. IEEE Micro. 2015 Jul 1;35(4):26-36. doi: 10.1109/MM.2015.71.

  • Energy-efficient pixel-arithmetic. Gilani SZ, Kim NS, Schulte M. IEEE Transactions on Computers. 2014 Aug 1;63(8):1882-1894. doi: 10.1109/TC.2014.2325827.

  • Low-cost per-core voltage domain support for power-constrained high-performance processors. Sinkar AA, Ghasemi HR, Schulte MJ, Karpuzcu UR, Kim NS. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014 Apr;22(4):747-758. doi: 10.1109/TVLSI.2013.2257900.

  • Automating stressmark generation for testing processor voltage fluctuations. Kim Y, John LK, Pant S, Manne S, Schulte M, et al. IEEE Micro. 2013;33(4):66-75. doi: 10.1109/MM.2013.70.
Recent Artistic Works
Collaboration
  • Madison Embedded Systems and Architectures Laboratory
  • Agere Systems, Lehigh Valley Central Campus, Kent E. Wires
  • Cukorova University, Mustafa Gok
  • Lehigh University
  • Koc University, Ahmet Akkas
  • IBM, Server and Technology group, Mark A. Erle
Research Tools
Research Facilities
E-mail Address [email protected]
Phone Number 608-262-0206
Current University UW–Madison
Department Electrical and Computer Engineering
Title Associate Professor
Other Appointments

Technical Advisory Board Member/Principal Consultant, Sandbridge Technologies

Address Line 1 4619 Engineering Hall
Address Line 2 1415 Engineering Drive
City Madison
State WI
Zip Code 53706
Bachelor's Degree B.S., UW–Madison, Electrical Engineering, 1991
Master's Degree M.S., University of Texas-Austin, Electrical Engineering, 1993
PhD Ph.D., University of Texas-Austin, Electrical Engineering, 1996
Other Degrees
Technologies Available for Licensing Decimal Floating-Point Adder

Processing Unit Having a Decimal Floating-Point Divider Using Newton-Raphson Iteration

Processing Unit Having Multioperand Decimal Addition