Researcher: Mikko Lipasti

Areas of Research Expertise
  • Applied physics
  • Computing
  • Information
  • Power
  • Improve performance and power efficiency
  • Reduce bandwidth and complexity
  • Computer architecture
  • Instruction-level parallelism
  • Compiler optimization
  • Runtime systems
  • Operating systems
  • Software techniques
  • Hardware techniques
  • Non-von neumann, biologically inspired computing systems modeled after the human neocortex
  • Combined hardware/software techniques for both improving the absolute performance of microprocessors and computer systems as well as reducing the complexity of implementation of such high-performance systems
  • Mask ever-increasing memory and inter-processor communication latencies in tomorrow's conventional von neumann-style computer systems
Web Site Mikko Lipasti's Department of Electrical and Computer Engineering Website
Curriculum Vitae (CV) Mikko Lipasti's CV
Current/Active Funding
  • WARF, 1999-2020, Sesquicentennial hire - Mikko Lipasti, ECE: Flexible funds
  • NSF, 2013-2017, SHF:Small:Reliable in-place execution for multicore processors
  • WARF, 2015-2016, WARF Tech_IEDR RA Match_Lipasti
  • WARF, 2016-2017, protoCRIB: a high performance, low power, and resilient processor prototype
  • WARF, 2015-2021, Retention_Lipasti_ECE
Issued Patent(s)
  • 6,487,640 - Memory access request reordering to reduce memory access latency, issued November 2002.
  • 6,487,639 - Data cache miss lookaside buffer and method thereof, issued November 2002.
  • 6,314,561 - Intelligent cache management mechanism, issued November 2001.
  • 6,219,780 - Circuit arrangement and method of dispatching instructions to multiple execution units, issued April 2001.
  • 5,778,233 - Method and apparatus for enabling global compiler optimizations in the presence of exception handlers within a computer program, issued July 1998.
USPTO Published Applications
  • 20130205295 - Parallel hardware hypervisor for virtualizing application-specific supercomputers, published August 2013.
Recent Publication(s)
  • Tag check elision. Zheng Z, Wang Z, Lipasti M. Proceedings of the International Symposium on Low Power Electronics and Design. 2015 Oct 13:351-356. doi: 10.1145/2627369.2627606.

  • A self-learning map-seeking circuit for visual object recognition. Shukla R, Lipasti M. Proceedings of the International Joint Conference on Neural Networks. 2015 Sep 28. doi: 10.1109/IJCNN.2015.7280676.

  • Adaptive cache and concurrency allocation on GPGPUs. Zheng Z, Wang Z, Lipasti M. IEEE Computer Architecture Letters. 2015 Jul;14(2):90-93. doi: 10.1109/LCA.2014.2359882.

  • COP: To compress and protect main memory. Palframan DJ, Kim NS, Lipasti M. Proceedings - International Symposium on Computer Architecture. 2015 Jun 17;13(1):682-693. doi: 10.1145/2749469.2750377.


View Mikko Lipasti's publications at Google Scholar.
Recent Artistic Works
Collaboration
  • PHARM
  • Cantin, Jason F. (International Business Machines Corp.)
Research Tools
Research Facilities
E-mail Address [email protected]
Phone Number 608-265-2639
Current University UW–Madison
Department Electrical and Computer Engineering
Title Professor
Other Appointments
Address Line 1 3621 Engineering Hall
Address Line 2 1415 Engineering Drive
City Madison
State WI
Zip Code 53706
Bachelor's Degree B.S., Valparaiso University, Computer Engineering, 1991
Master's Degree M.S., Carnegie Mellon University, 1992
PhD Ph.D., Carnegie Mellon University, 1997
Other Degrees
Technologies Available for Licensing